EEspice is an open-source, SPICE-compatible circuit simulation framework optimized for performance. As modern analogue/mixed-signal design increasingly relies on optimization-in-the-loop flows such as AI and LLM-based sizing agents that repeatedly invoke SPICE, efficient, accurate high-performance simulators have become an indispensable foundation for modern integrated circuit (IC) design.

However, the computational cost of evaluating nonlinear models, particularly for BSIM models, remains a significant bottleneck. In standard parallelization approaches, devices such as transistors are easily distributed across processors. The subsequent stamping phase, where each device's contributions are added to the shared system matrix, often creates a bottleneck. Because multiple processor cores compete to update the same matrix elements simultaneously, the system is forced to process tasks one at a time to avoid errors.

EEspice addresses this with a modular architecture that decouples device model evaluation into independently replaceable kernels, enabling a parallel stamping strategy. It partitions MOSFET instances into independent color groups using graph coloring, which can be processed in parallel. On a 64-core workstation, the proposed approach achieves up to 45x speedup over single-thread performance when conflicts are low.

Find out more at eelab-dev/EEspice and eespice.eelab.dev